Method for electrochemical etching of semiconductor material using positive potential dissolution (PPD) in HF-free solutions

ABSTRACT

A method for electrochemical etching of a semiconductor material using positive potential dissolution (PPD) in hydrofluoride (HF)-free solutions. The method includes subjecting one of: a polished material; and an as-cut semiconductor material to an etching solution. The method also includes positive biasing at atypically highly positive (anodic) potentials. The specifically controlled and directed illumination of the positively biased semiconductor material surface contacted and wetted by the etching solution significantly increases the value of the anodic current density (A/cm 2 ) of the semiconductor material. The application of positive biasing at atypically highly positive (anodic) potentials, is combined with specifically controlling and directing illumination by light of the semiconductor material surface contacted and wetted by the etching solution. This is done for a necessary and sufficient period of time to enable a positive synergistic effect on the rate and extent of etching of the semiconductor material, and that formed therefrom.

FIELD OF THE INVENTION

The present invention relates to methods for etching semiconductormaterials based on applying positive (anodic) potentials duringconditions of wet etching in hydrogen fluoride free (HF-free) solutions,and more particularly, to a method for forming, polishing and texturinga semiconductor material using the technique of positive potentialdissolution (PPD).

BACKGROUND OF THE INVENTION

The development of a simple, reliable, inexpensive and environmentallyfriendly process of silicon etching is of significant practicalimportance to the semiconductor industry. Various methods of siliconetching were developed in the last three decades

Typically, existing silicon etching methods, involving polishing andtexturing, based on PPD is performed in media containing hydrofluoricacid (HF). The etching is combined with the process of photolithography.Such an electrochemical technique involves combining positive (anodic)biasing of the silicon that is exposed to (contacted and wetted by) anaggressive HF etching solution, with possible illumination of thepositively biased exposed silicon surface, and is reasonably effectivefor increasing control and the rate of the silicon etching/texturingprocess. However, the use of media containing HF is undesirable becauseit is accompanied by serious environmental issues relating to itshandling and disposal.

Slow silicon texturing based on anisotropic etching is usually performedin HF-free alkaline solutions, for example, NaOH or KOH solutions,during relatively long term exposure of the silicon surface at opencircuit potential (OCP), without electrical biasing. This is becausepositive (anodic) biasing of silicon in alkaline solutions results ininactivation and/or deactivation of the silicon surface, so thatetching, and therefore, texturing or polishing stops. Typical etchingrates in KOH at open circuit are below 1 microns/min {e.g., R. A Wind etal., J. Phys. Chem. B, 106, 1557-1569 (2002), I. Zubel and M.Kramkowska, Sensors and Actuators A, Physical, A93(2), 138-147 (2001)}.Attempting to increase the rate of etching and texturing of the siliconby using positive (anodic) biasing of the exposed silicon surfaceresults in working in a region within which the treated material(silicon and/or metal) becomes passive or inactivated, or activelydissolves and becomes deactivated. Thus, except when etching/texturingsilicon in HF solutions, positive (anodic) biasing has not been in use.

Thus, it would be highly advantageous to have a method for fast etching(polishing/texturing) a semiconductor material using the technique ofpositive potential dissolution (PPD), based on applying atypicallyhighly positive (anodic) potentials during conditions of wet etching,and continued etching (polishing/texturing) of a semiconductor materialformed therefrom. Such a method is generally commercially applicable toa variety of related fields and sub-fields.

SUMMARY OF THE INVENTION

Accordingly, it is a principal object of the present invention toprovide a method for fast etching (polishing/texturing) a semiconductormaterial using the technique of positive potential dissolution (PPD) ata rate of at least 5 microns/min.

It is another object of the present invention to provide a method foretching (polishing/texturing) using a technique based on applyingatypically highly positive (anodic) potentials during conditions of wetetching, and an etched (polished/textured) semiconductor material formedtherefrom.

It is a further object of the present invention to provide a method foretching (polishing/texturing) a semiconductor material, comprisingsimple and inexpensive steps.

It is a further object of the present invention to provide a method forfast etching (polishing/texturing) a semiconductor material, usingnon-toxic chemicals.

The method of the present invention provides a technique of positivepotential dissolution (PPD), based on applying positive (anodic)potentials higher than +10 volts relative to a standard referenceelectrode, such as a standard calomel electrode (SCE). In particular,application is made of a range of potentials between about plus 10 voltand plus 750 volts relative to a standard reference electrode, such as aSCE, during conditions of wet etching. Application of the potential maybe combined with illumination of the positively biased exposed siliconsurface, allowing silicon etching. The rate of silicon etching(texturing/polishing) in alkaline media, for example, KOH solutions,could be significantly increased by using high positive (anodic)biasing, above passive potentials of the silicon that is exposed to(contacted and wetted by) the alkaline etching solution, with or withoutillumination of the positively biased exposed silicon surface.

The present invention is generally applicable to a wide variety ofsemiconductor materials, including, for example, different types ofpolished semiconductor materials, and different types of “‘as cut’”unpolished semiconductor materials. The present invention is generallyapplicable to a variety of different fields and sub-fields requiring orinvolving polishing or texturing the surface of semiconductor materialsand polished or textured semiconductor materials formed therefrom, andis particularly applicable to the field of microelectronics,micro-electromechanical systems (MEMS) and the manufacturing of solarcells or photovoltaic panels from semiconductor materials, involvingtexturing surfaces of the semiconductor materials for the objective ofdecreasing reflectance of incident sunlight away from the semiconductormaterial surfaces.

The present invention relates to a method for etching(polishing/texturing) a semiconductor material using the technique ofpositive potential dissolution (PPD), based on applying atypicallyhighly positive (anodic) potentials during conditions of wet etching,and a textured/polished semiconductor material formed. The rate andextent of etching of the semiconductor material, and therefore, thedegree of polishing and texturing of semiconductor material formed, arecontrollable and significantly influenced by the several primaryoperating conditions and parameters of the positive potentialdissolution (PPD) technique: the type of the semiconductor material;semiconductor crystallinity, electrolyte concentration, temperature andflow rate of the etching solution; magnitude and duration of thepositive biasing; and by the semi-conductor type and crystallographicorientation, light intensity of at least 0.01 watts per cm², or lessthan 0.01 watts per cm², respectively), wavelength and duration ofillumination incident upon the positive biased semiconductor materialsurface exposed to the etching solution. This illumination requirementis not essential in all cases.

The method is specifically designated for:

-   -   a stand-alone method for etching (polishing or texturing) a        semiconductor material;    -   as part of a more encompassing multi-stage method for processing        or manufacturing a semiconductor material; or    -   combined in a bath where the counter electrode is a        semiconductor as well, and allowing on this counter electrode a        NPD process as outlined in U.S. Pat. No. 6,521,118 and U.S.        patent application Ser. No. 10/750,969, the disclosures of which        are herein incorporated by reference.

In a preferred embodiment of the present invention, the positivepotential dissolution (PPD) texturing method features subjecting apolished material, or an as-cut, semiconductor material to an etchingsolution. The method also includes positive biasing at atypically highlypositive (anodic) potentials, more positive than plus 10 volts relativeto a standard reference electrode. Specifically controlling anddirecting illumination by light, preferably, processed non-ambientlight, incident upon the positively biased polished/as-cut semiconductormaterial surface contacted and wetted by the HF-free etching solution.The specifically controlled and directed illumination of the positivelybiased semiconductor material surface contacted and wetted by theetching solution significantly increases the value of the anodic currentdensity (A/cm²) of the semiconductor material.

Accordingly, in this preferred embodiment, the positive biasing atatypically highly positive (anodic) potentials, preferably but notessentially, combined with specifically controlling and directedillumination by light of the semiconductor material surface contactedand wetted by the etching solution, for a period of time, corresponds toa positive synergistic effect on the rate and extent of etching of thesemiconductor material, and therefore, on the type of etchedsemiconductor material formed therefrom.

Secondly, in the case of an “as cut” unpolished semiconductor material,the positive potential dissolution (PPD) etching method featuressubjecting the material to an etching solution and positive biasing atatypically highly positive (anodic) potentials, during non-specificallycontrolled and, preferably but not essentially, directed illumination byunprocessed surrounding or background ambient light, incident upon thepositively biased “as cut” unpolished semiconductor material. Thenon-specifically controlled and directed illumination of the negativelybiased “as cut” unpolished semiconductor material has no measurableaffect upon the value of the anodic current density (A/cm²) of the “ascut” unpolished semiconductor material, or upon the rate and extent ofetching of the “as cut” unpolished semiconductor material, andtherefore, upon the type of etched “as cut” unpolished semiconductormaterial formed.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to understand the invention and to see how it may be carriedout in practice, a preferred embodiment will now be described, by way ofnon-limiting example only, with reference to the accompanying drawings,in which:

FIG. 1 is a graph of the effect of applied potential on etch rate andcurrent density of p-type Si [(100) surface orientation] in 24 wt % KOH,constructed in accordance with the principles of the present invention;

FIG. 2 is a graph of current density vs. time, with p-type Si [(100)surface orientation] in 24 wt % KOH at different applied potentials,constructed in accordance with the principles of the present invention;

FIG. 3 is a graph of the effect of applied potential on an etch rate ofp-type Si [(100) surface orientation] in solution with different KOHconcentrations, constructed in accordance with the principles of thepresent invention;

FIG. 4 is a graph of the effect of KOH concentration on an etch rate ofp-type Si [(100) surface orientation] at the applied potential of 50 V,constructed in accordance with the principles of the present invention;

FIGS. 5 a-5 d are atomic force microscope (AFM) images of “as cut”silicon wafer after positive potential dissolution (PPD) silicon andpresenting the capability to polish [an] as-cut surfaces;

FIGS. 6 a and 6 b are High Resolution Scanning Electron Microscope(HRSEM) images of an “as cut” surface and polished surface via PPD; and

FIGS. 7 a and 7 b are HRSEM images of polished p type 110 which wastextured via PPD.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The principles and operation of a method and an apparatus according tothe present invention may be better understood with reference to thedrawings and the accompanying description, it being understood thatthese drawings are given for illustrative purposes only and are notmeant to be limiting.

FIG. 1 is a graph of the effect of applied potential 110 on the etchrate 120 and current density 130 of p-type Si [(100) surfaceorientation] in 24 wt % KOH, constructed in accordance with theprinciples of the present invention. Silicon is being rapidly etched insolutions (e.g., aqueous, non-aqueous, molten salts and inorganic media)under an applied positive potential higher than 10 V. FIG. 1 presentsboth etching rate 120 and current density 130 of p type silicon in asolution of 24 wt % KOH performed in the dark. Etching rates 120,measured by weight loss evaluation, and measured current density 130 areseen to generally coincide and present similar profiles. It can also beseen that both etching and current increase as potential is increasedfrom 20 V [vs. standard calomel electrode (SCE) reference electrode].Below this value neither etching nor current are recorded. Shifting thepotential to values higher than 25 V causes a dramatic increase in etchrate 120 and current density 130 measured. Etching rate 120 increasesfrom a value of less than 1 micro-meter/min., at 25 V, to 10microns/min. at a potential of 40 V. The same trend is observed withcurrent density 130 measured at the different potentials. At a potentialof 25 V measured current density 130 was recorded as less than 25mA/cm², while at a potential of 40 V current density 130 soared to avalue of 3.5 A/cm².

FIG. 2 is a graph of current density vs. time, with p-type Si [(100)surface orientation] in 24 wt % KOH at different applied potentials,constructed in accordance with the principles of the present invention.FIG. 2 presents current time transients recorded at different positivepotentials 211-214 (between 28 and 45 V), with the use of p-type siliconpolarized in 24 wt % KOH at room temperature. As can be seen, at 28 V211, the current 220 recorded increased initially to 100 mA/cm², andwithin a time 230 of 3 minutes fades to a minimum value of 20 mA/cm².Once potential 210 is increased to 35 V 212, current 220 at t+0 soaredto 2.5 A/cm², slowly decreasing to a plateau value of 1.6 A/cm². Atpotentials of 40 V 213 and 45 V 214, current 220 measured are 4 and 5A/c m², respectively. Thus, as potential 210 increases, response current220 increases dramatically as well.

FIG. 3 is a graph of the effect of applied potential 310 on an etch rate320 of p-type Si [(100) surface orientation] in solution with differentKOH concentrations 331-335 ranging between 4 and 32 wt %, constructed inaccordance with the principles of the present invention. As can be seen,PPD can be “ignited” even with a low content of KOH electrolyte. Thiswould occur at higher potentials, above 35 V. On the other hand with theuse of 32 wt % electrolyte concentration 335, the PPD etching of thesilicon surface starts at a potential of 20 V, at a much earlier stage.Thus, as one can observe, as the concentration of the alkaline insolution increases, the potential at which PPD initiates is lower.Etching rates 320 of more than 20 microns/min were recorder at apotential of 55 V in a solution containing 32 wt % 335.

FIG. 4 is a graph of the effect of KOH concentration 410 on an etch rate420 of p-type Si [(100) surface orientation] at the applied potential of50 V, while performing PPD, constructed in accordance with theprinciples of the present invention. As one can see, at a potential of50 V and a concentration of 50 wt %, an etching rate of more than 25microns/min 430 was measured. Thus, it can be seen that the dependenceof etching rate on the alkaline concentration is linear in solutionscontaining more that 10 wt % KOH.

FIGS. 5 a-5 d are atomic force microscope (AFM) images of “as cut” andpositive potential dissolution (PPD) silicon presenting the capabilityto polish an as-cu surface, after PPD at 130 sec, 55V and aconcentration of 32% KOH. Dimensions are indicated for the x-axis 510 inmicrometers, the y-axis 520 in micrometers and the z-axis 510 innanometers.

FIGS. 6 a and 6 b are High Resolution Scanning Electron Microscope(HRSEM) images of an “as cut” surface and polished surface,respectively, via PPD. Thus, FIG. 6 a illustrates a configurationsubsequent to positive potential dissolution (PPD) silicon (100),presenting the capability to polish an as-cu surface, after PPD 610 at130 sec, 55V and a concentration of 32% KOH. FIG. 6 b is an “as cut”reference 600, before application of PPD.

FIGS. 7 a and 7 b are HRSEM images of polished p type 110 which wastextured via PPD. FIG. 7 a illustrates HRSEM of pristine polishedsilicon (100) subsequent to positive potential dissolution (PPD) 700,presenting the ability to texture a polished surface within 5 minutes,after PPD process at 40 V in a solution containing 50% KOH. FIG. 7 billustrates a “zoom,” close-up view of the features of the texturedmaterial 710.

It is to be understood that the phraseology and terminology employedherein are for the purpose of description, and should not be regarded aslimiting.

It is important, therefore, that the scope of the invention is notconstrued as being limited by the illustrative embodiments set forthherein. Other variations are possible within the scope of the presentinvention as defined in the appended claims and their equivalents.

1. A method for electrochemical etching of a semiconductor materialusing positive potential dissolution (PPD) in hydrogen fluoride(HF)-free alkaline etching solutions, said method comprising: subjectingone of: a polished material; and an as-cut semiconductor material to anetching solution; positively biasing said material at atypically highlypositive (anodic) potentials; and specifically controlling and directingillumination by light incident upon the positively biasedpolished/as-cut semiconductor material surface contacted and wetted bythe HF-free etching solution, such that the specifically controlled anddirected illumination of the positively biased semiconductor materialsurface contacted and wetted by the etching solution significantlyincreases the value of the anodic current density (A/cm²) of thesemiconductor material, and such that the application of positivebiasing at atypically highly positive (anodic) potentials, combined withspecifically controlling of the semiconductor material surface contactedand wetted by the etching solution, is applied for a necessary andsufficient period of time to enable a positive synergistic effect on therate and extent of etching of the semiconductor material, and therefore,on the type of etched semiconductor material formed therefrom.
 2. Themethod of claim 1, wherein said potential is more positive than plus 10volts relative to a standard reference electrode.
 3. The method of claim2, wherein the rate of silicon etching is significantly increased byusing such highly positive (anodic) biasing, above passive potentials ofthe silicon that is exposed to (contacted and wetted by) the alkalineetching solution.
 4. The method of claim 1, wherein said application ofpositive biasing at atypically highly positive (anodic) potentials, isfurther combined with directing illumination by light.
 5. The method ofclaim 4, wherein said light is processed non-ambient light.
 6. Themethod of claim 1, as applied to microelectronics.
 7. The method ofclaim 1, as applied to micro-electromechanical systems (MEMS).
 8. Themethod of claim 1, as applied to the manufacturing of solar cells fromsemiconductor materials, involving texturing surfaces of thesemiconductor materials for the objective of decreasing reflectance ofincident sunlight away from the semiconductor material surfaces.
 9. Themethod of claim 1, as applied to the manufacturing of photovoltaicpanels from semiconductor materials, involving texturing surfaces of thesemiconductor materials for the objective of decreasing reflectance ofincident sunlight away from the semiconductor material surfaces.
 10. Themethod of claim 1, as part of a more encompassing multi-stage method forprocessing or manufacturing a semiconductor material.
 11. The method ofclaim 1, wherein said subjecting of a semiconductor material to anetching solution is combined in a bath where the counter electrode is asemiconductor as well, and further comprising negative biasing of saidcounter electrode in a negative potential dissolution (NPD) process. 12.The method of claim 1, wherein said rate of etching of the semiconductormaterial and the type of etched semiconductor material formed therefrom,is at least 5 microns/min.
 13. A system for electrochemical etching of asemiconductor material using PPD in hydrogen fluoride (HF)-free alkalineetching solutions, said system comprising: means for subjecting one of:a polished material; and an as-cut semiconductor material to an etchingsolution; means for positively biasing at atypically highly positive(anodic) potentials; and means for specifically controlling anddirecting illumination by light incident upon the positively biasedpolished/as-cut semiconductor material surface contacted and wetted bythe HF-free etching solution, such that the specifically controlledillumination of the positively biased semiconductor material surfacecontacted and wetted by the etching solution significantly increases thevalue of the anodic current density (A/cm²) of the semiconductormaterial, and such that the application of positive biasing atatypically highly positive (anodic) potentials, for a necessary andsufficient period of time to enable a positive synergistic effect on therate and extent of etching of the semiconductor material, and therefore,on the type of etched semiconductor material formed therefrom.
 14. Thesystem of claim 13, wherein said application of positive biasing atatypically highly positive (anodic) potentials is further combined withdirecting illumination.